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vhdl =>什么意思 跟<=有什么区别?

vhdl =>什么意思 跟<=有什么区别?

<=是Signal的赋值,=>是用于port map 子模块的例化比如:U2 : ram1 PORT MAP ( clka =>弊悄 ram2_clk, wea => wren2&"", addra => wr_addr2, dina =>轮卜答 "0000"& ram2_data, clkb =>腊慧 DSP_AMS3 AND DSP_ARD, addrb => DSP_ADDR(13 downto 0), doutb => ram2_q );在 case—when 语句里用到过例如:case s is when "00" => y<=a0; when "01" => y<=a1; when others=> y<=a2;